Honored Contributor
Honored ContributorWell, for a start, I would ditch the clk_reg signal all together. Its going to make things break. Just clock everything with the system clock.
The state_read process is also missing a lot of signals from the sensitivity list, so this will cause a sim/synth missmatch as the sensitivity list is ignored for synth, and logic created from it. ALL signals read in the process should be in the list (you are missing state, wr_reg, addr_reg, memory). Also, as data and the vars are not set in ALL states (ie, you have no else cases) you will create latches, which cause problems for timing. Why have you set the sclk to clk_reg? what is the system clock speed? what is the SPI clock rate?
