ModelSim simulation result is different to run in real FPGA

The test bench : adc01_tb.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity adc01_tb is
end adc01_tb;
architecture behavior of adc01_tb is
	component adc01
	 port (
		addr   : in std_logic_vector (6 downto 0);      -- address bus, 7-bit
		data   : inout std_logic_vector (12 downto 0);  -- data bus
		rd     : in std_logic;                          -- read me, active low
		wr     : in std_logic;                          -- write me, active low
		bs     : in std_logic;                          -- board select, active low
		--
		hwst   : in std_logic;                          -- hardware start command
		--
		convst : out std_logic;                         -- conversion start
		-- stby   : out std_logic;                         -- standby mode, active low
		reset  : out std_logic;                         -- reset ADCs, active high,pulse width > 50 ns
		sclk   : out std_logic;                         -- SPI SCLK
		fs     : out std_logic;                         -- SPI SS, active low, ADCs' frame synchronization
		miso   : in std_logic_vector (63 downto 0);     -- SPI MISO
		busy   : in std_logic;                          -- DAC busy, active high
		--
		clk    : in std_logic	-- system clock
	 );
	end component;
--	signal addr   : std_logic_vector (7 downto 0) := (others => '0');
	signal addr   : std_logic_vector (6 downto 0);
	signal data   : std_logic_vector (12 downto 0);
	signal rd     : std_logic := '1';
	signal wr     : std_logic := '1';
	signal bs     : std_logic := '1';
	--
	signal hwst   : std_logic := '1';
	--
	signal convst : std_logic;
	-- signal stby   : std_logic;
	signal reset  : std_logic;
	signal sclk   : std_logic;
	signal fs     : std_logic;
	signal miso   : std_logic_vector (63 downto 0) := (others => '0');
	signal busy   : std_logic := '0';
	--
	signal clk    : std_logic := '0';
	signal test_data_1 : std_logic_vector (31 downto 0) := x"040003ff";
	-- Special purpose Addresses --
	constant ADDR_STATUS : integer := 0;
	-- constant ADDR_CMD  : integer := 0;      -- The command register
	-- Command --
	constant CMD_CNVST  : integer :=    1;  -- Start conversion
	constant CMD_RESET  : integer := 8191;  -- Reset ADCs, for 12-bit data bus
	constant CLK_PERIOD : time := 40 ns; -- 25 MHz clock
begin
	uut : adc01 port map (
		addr   => addr,
		data   => data,
		rd     => rd,
		wr     => wr,
		bs     => bs,
		--
		hwst   => hwst,
		--
		convst => convst,
		-- stby   => stby,
		reset  => reset,
		sclk   => sclk,
		fs     => fs,
		miso   => miso,
		busy   => busy,
		--
		clk    => clk
	);
	clock : process
	begin
		clk <= '0';
		wait for CLK_PERIOD/2;
		clk <= '1';
		wait for CLK_PERIOD/2;
	end process;
	stimulus : process
	begin
		-- Reset
		-- wait for 11 ns;
		-- addr <= std_logic_vector(to_unsigned(ADDR_CMD, addr'length));
		data <= std_logic_vector(to_unsigned(CMD_RESET, data'length));
		wait for 13 ns;
		bs   <= '0';
		wr   <= '0';
		wait for 50 ns;
		wr   <= '1';
		bs   <= '1';
		wait for 100 ns;
		-- Start convert
		data <= std_logic_vector(to_unsigned(CMD_CNVST, data'length));
		wait for 13 ns;
		bs   <= '0';
		wr   <= '0';
		wait until convst='1';
		wait for 25 ns;  -- -+
		busy <= '1';	 --  |
		wait for 50 ns;  -- -+- The max convertion time is 1.33 us
		busy <= '0';
		
		wr   <= '1';
		bs   <= '1';
		wait for 100 ns;
		-- Reset
		wait for 200 ns;
		data <= std_logic_vector(to_unsigned(CMD_RESET, data'length));
		wait for 50 ns;
		bs   <= '0';
		wr   <= '0';
		wait for 50 ns;
		wr   <= '1';
		bs   <= '1';
		wait for 100 ns;
		-- Start convert
		data <= std_logic_vector(to_unsigned(CMD_CNVST, data'length));
		wait for 13 ns;
		bs   <= '0';
		wr   <= '0';
		-- or hardware start
		--hwst <= '0';
		--wait for 50 ns;  -- -+
		wait until convst='1';
		wait for 25 ns;    -- -+
		busy <= '1';	   --  |
		wait for 25 ns;    --  |
		wr   <= '1';       --  |
		--hwst <= '1';     --  |
		wait for 1280 ns;  -- -+- The max convertion time is 1.33 us
		busy <= '0';
		wait until fs='0';
		wait for 12 ns; --TDMSB
		for i in 0 to miso'length -1 loop
			miso(i) <= test_data_1(31);
		end loop;
		test_data_1 <= test_data_1(30 downto 0) & '0';
		for j in 0 to 30 loop
			wait until sclk='0';
			wait for 17 ns; -- TPDDO
			for i in 0 to miso'length -1 loop
				miso(i) <= test_data_1(31);
			end loop;
			test_data_1 <= test_data_1(30 downto 0) & '0';
			wait until sclk='1';
		end loop;
		wait for 100 ns;
		-- Read data
		data <= (others => 'Z');
		addr <= std_logic_vector(to_unsigned(ADDR_STATUS, addr'length));
		wait for 7 ns;
		bs <= '0';
		rd <= '0';
		wait for 50 ns;
		rd <= '1';
		wait for 50 ns;
		for i in 0 to 127 loop
			addr <= std_logic_vector(to_unsigned(i, addr'length));
			wait for 8 ns;
			rd <= '0';
			wait for 50 ns;
			rd <= '1';
			wait for 50 ns;
		end loop;
		wait for 200 ns;
		bs   <= '1';
		wait for 2 us;
	end process;
end;