ModelSim simulation result is different to run in real FPGA

Are you using multiple clocks? Eg., is your shift-register shifting based on the SPI clock or an FPGA clock?

If the FPGA is acting as an SPI slave, and the SPI clock is much slower than the FPGA clock (or an FPGA clock generated by a PLL), then you would typically route the SPI clock through a synchronizer (dual DFF), and then through edge-detection logic, for SPI rising-edges and SPI falling-edges. Depending on the device you are communicating with, you would typically shift in on the rising-edge, and out on the falling-edge. This does not require two shift-registers, one will do; shift in on the rising-edge pulse, and update an output register on the falling-edge.

If you have not implemented synchronization correctly, then you will see a simulation vs hardware mismatch.

You will also see a mismatch if you have poor signals on your hardware, eg. an SPI clock routed to multiple devices can have reflections which cause the clock-edge to be non-monotonic. If your FPGA was acting as an SPI slave, with the SPI clock as an input, a small glitch on the clock can cause the FPGA (which is fast) to think it is seeing two clock edges.

Note that you can use SignalTap II to look at the input signals inside the FPGA (though your device may be too old to support SignalTap II ....)

Cheers,

Dave