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I implemented a LVDS receiver(factor=2) in QUATUS 9.0 written in verilog and VHDL respectively,and timing result both tells me that i can get the correct result for a 1Gbps input.
What's strange,in modelsim se 6.0 and modelsim-altera 6.4a,I can get the correct result for the VHDL edition for a 500Mbps input;but i can't get the correct result for the verilog editon for the same 500Mbps input!!
Has anyone ever encoutered this problem? Why?
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When you say timing result, do you mean the result from the timing analyser? This has nothing to do with functionality, and only tells you that the logic can be clocked at a certain frequency to maintain data intergrity. It doesnt tell you that the design will actually work or not. Thats what simulation (modelsim) is there for.
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