Modelsim Simualtion

Hi ,

I have a very simple design in Quartus Web Pack ver 11.0 , and with it i have Modelsim-Altera Starter ver 6.6d. I dont see any output or response of the design when i run RTL simualtion .

I have used the same vhdl files and run the simulation in Modelsim ver 6.2 SE and i see results as expected ???

I have checked the mapping of lib using vmap it is ok .

What is the problem ???

Please find attached the screen shots and the project.

Thanks in advance