Modelsim sim force ariables in a two-dimensional array

You may find the answer below:

For Verilog:

If you have a two-dimensional array like this:

reg [7:0] mem [0:3]; // 4x8-bit array

For a multi-bit element inside an array:

reg [3:0] mem [0:3][0:1]; // 4x2 array of 4-bit registers

For VHDL:

If you have a two-dimensional array:

type mem_array is array (0 to 3, 0 to 1) of std_logic_vector(3 downto 0);

signal mem : mem_array;