ModelSim reports type mismatch in SOPC Builder generated Code

Hello,

I have a problem simulating my SOPC builder generated system. If I compile my design in ModelSim SE 6.5b I get the following errors:

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# ** Error: C:/Workspace/BB_CMMB/cmmb_remux.vhd(15323): (vopt-1133) Type mismatch for port "slave_address" in component "clock_crossing_0" when binding to entity "clock_crossing_0".# ** Error: C:/Workspace/BB_CMMB/cmmb_remux.vhd(15323): (vopt-1133) Type mismatch for port "slave_nativeaddress" in component "clock_crossing_0" when binding to entity "clock_crossing_0".# ** Error: C:/Workspace/BB_CMMB/cmmb_remux.vhd(15323): (vopt-1133) Type mismatch for port "master_nativeaddress" in component "clock_crossing_0" when binding to entity "clock_crossing_0".# ** Error: C:/Workspace/BB_CMMB/clock_crossing_0.vhd(275): Vopt Compiler exiting

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The corresponding code is the following

  --the_clock_crossing_0, which is an e_ptf_instance
  the_clock_crossing_0 : clock_crossing_0
    port map(
      ...
      master_nativeaddress(0) => clock_crossing_0_m1_nativeaddress,
      ...
      slave_address(0) => clock_crossing_0_s1_address,
      ...
      slave_nativeaddress(0) => clock_crossing_0_s1_nativeaddress,
      ...
    );

with the following port/signal definitions

                ...
                signal clock_crossing_0_m1_nativeaddress :  STD_LOGIC;
                ...
                signal clock_crossing_0_s1_address :  STD_LOGIC;
                ...
                signal clock_crossing_0_s1_nativeaddress :  STD_LOGIC;
                ...

and

component clock_crossing_0 is 
           port (
                 -- inputs:
                    ...
                    signal slave_address : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
                    ...
                    signal slave_nativeaddress : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
                    ...
                 -- outputs:
                    ...
                    signal master_nativeaddress : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
                    ...
                 );
end component clock_crossing_0;

I dont have problems compiling the design with Quartus II 9.1SP1. So the only workaround I see is to compile it in Quartus II and use the generated *.vho in ModelSim.

Any other suggestions ?

Thanks in advance