ModelSim Random Input Stimulus?

A testbench usually has no inputs and no outputs (ie. no port declaration), it justs generates the IO for the unit under test. You would not compile a testbench in quartus, and it would not go into the FPGA.

my testbenches usually start like this:

entity my_ent_TB is
end entity my_ent_TB;
architecture test of my_ent_TB is 
begin
  ....
end architecture my_ent_TB;

VHDL supports ALOT of stuff that you cant compile in quartus, which is intended exactly for simulation. For example, to generate a clock, you can do this:

clk <= not clk after 10 ns; --a 100MHz clk.

and for specified inputs:

input <= '1', '0' after 1 us, '1' after 2us, '0' after 5us ; --etc.

or for more complicated things (like random number input procedure above):

assume input_slv is an 8 bit bus:

process
  variable seed1, seed2 : positive := 1587437; --any number will do. Different seed value changes the sequence.
  variable input_int    : integer;
begin  
  wait until rising_edge(clk);
  
  rand_int(seed1, seed2,  0, 255, input_int);
  
  input_slv <= std_logic_vector( to_unsigned( input_int, 8));
end process;