Modelsim problems while simulating Dual Port SRAM

Hi, I've written a vhdl file that describes True Dual Port SRAM in the same manner as recommended in the Quartus style guide. I was using this same file in the past for single port SRAM and it worked fine in ModelSim(MS) simulations. Now when I add another port, the writes work incorrectly in the MS waveform and the data_out is all 'U' with some random bits written correctly. Another funny part is when I comment out the second port from the SRAM file the simulation is fine and the writes work. I'm using all the same files both times, and I've attached them, as well as a picture of the MS wave:

cache_set.vhd : the SRAM file

cache_set_tb : the testbench I'm using for MS

params : some constants used in the project

http://www.alteraforum.com/forum/attachment.php?attachmentid=10406&stc=1