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Altera_Forum
Honored Contributor
Honored Contributormodelsim problem regarding input initialization
Hello, i recently encountered a problem when simulating in modelsim which was with the outputs not resposnding to the inputs. Then once i initialized all the inputs the outputs responded normal...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- To voidptr. Your post only applies to vhdl. The op might be using verilog where uninitialized signals default to X. Also I think most of what you pirated doesn't really ally to the ops problem. To the OP. Post your code. Your problem sounds like a code error. --- Quote End --- Tricky, I agree that I wrote purely from a vhdl perspective. I am not as experienced with verilog, but I think the concepts should be similar? The OP's second question was a fairly general question about whether it is a good idea to initialize all inputs. I argued that it is, and I tried to come up with some examples from the top off my head to support my point of view. If you disagree or don't like my answer, that's fine, but please don't be so quick at accusing me of pirating. I write my own answers, and if I quote someone else I always try to specify the source.
