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Altera_Forum
Honored Contributor
10 years agoA simple reason is that the register that you declared did not experience a proper reset and as such it would drive X during the start of your simulation.
Since you implement register with active low reset, the negedge condition of the rstn is not met when you tied it to 1'b1 (set it high at the start of simulation). As such, the register will drive out X until the D pin input is stable. Negedge condition require a transition of low to high in order to take effect.