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Altera_Forum
Honored Contributor
Honored Contributormodelsim problem regarding input initialization
Hello, i recently encountered a problem when simulating in modelsim which was with the outputs not resposnding to the inputs. Then once i initialized all the inputs the outputs responded normal...
Altera_ForumHonored Contributor
Honored ContributorTo voidptr. Your post only applies to vhdl. The op might be using verilog where uninitialized signals default to X. Also I think most of what you pirated doesn't really ally to the ops problem.
To the OP. Post your code. Your problem sounds like a code error.
