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In this design the values of X,Yand Z will not go outside the boundaries by design.
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Designs need to be validated. Since your sim indicates that lxn is going outside of its defined range it suggest that things aren't quite right by design after all.
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Now in this case X,Y and Z propagate through a number of registered stages. So even if X gets registered ad a different moment, inducing the 'dreaded' delta cycle we either have X being 0 or 226 and Y being either 0 or -113.
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That might all be true, but you haven't posted any code that shows how X and Y are actually generated so nobody else can really verify this (which is fine), but it means that suggestions can be offered for things for you to look at. What I haven't heard in return is whether you have verified in the list window that X and Y really are changing on the same simulation delta cycle, and while you stated that X = 226 and Y = -113 at the point of the failure, it's not clear what it was prior to that...
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No combination of either X + or - Y/4 or Y + or - X/4 goes outside the -256 to + 255 range? Second as it is a registered design only the value at the required setup time is of interest. I agree that if at that moment the value is out of range an error is warranted, before that time a warning would do. Although this is RTL simulation there is no notion of setup time and no delta (this being VHDL code)?
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This has nothing to do with setup times. The error reported is "Value 261 for lxn is out of range -256 to 255" which simply means that the signal had a defined range and there was an attempt to assign a value that is outside of that range...that is an error.
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Am I correct that your testbench avoids a delta cycle as X and Y change at exactly the same moment? What will happen if you induce a delta cycle by delaying the change of e.g. Y?
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Nothing...but that may not be the same sequence of X,Y pairs that you are simulating. Just prior to the X,Y that causes the failure there must have been a different X,Y pair. Perhaps the previous X and the current Y exist for one simulation delta cycle and that causes the error.
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I did put all stages in the list window and a saw nothing that would have generated the 261 value.
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My question was do X and Y change on the exact same simulation delta cycle? Perhaps it would simply be better for you to run the simulation to the point of the failure and simply copy/paste the last few lines of the list window since we don't seem to be getting very far.
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On my next 'try' I will add the report statement.
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That should produce useful information
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I will then switch to Timing SImulation. As this design is heavily registered, most vital signals will be preserved and will allow a reasonably good inspection of the internals.
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The timing sim will produce nothing of value as it relates to this problem. The reason is that the timing sim is based on the synthesized logic which has no notion of integer range boundaries. If your design happens to overflow, the typical response is that the values will simply wrap around because arithmetic operators get transformed to boolean logic. Boolean logic does not have integer ranges so there can be no error of this type to report...regardless of what design it is.
Kevin Jennings
Honored Contributor
