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Just because something compiles doesn't mean that there will not be a runtime error. The ranges for X and Y and the function impliemented by lxn allow for lxn to be out of the range that you stated which implies there is the possibility for exactly the runtime error that you are seeing.
For that error to never occurs implies that the way that X and Y are generated in your system must operate in such a way that they never happen to hit the condition where the computation of lxn is ever out of range, even for a single simulation delta cycle.
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You're quite right about the compilation itsel being no guarantuee, but in VHDL if you can compile without warnings, the chances are quite good.
In this design the values of X,Yand Z will not go outside the boundaries by design.
Now in this case X,Y and Z propagate through a number of registered stages. So even if X gets registered ad a different moment, inducing the 'dreaded' delta cycle we either have X being 0 or 226 and Y being either 0 or -113. No combination of either X + or - Y/4 or Y + or - X/4 goes outside the -256 to + 255 range? Second as it is a registered design only the value at the required setup time is of interest. I agree that if at that moment the value is out of range an error is warranted, before that time a warning would do. Although this is RTL simulation there is no notion of setup time and no delta (this being VHDL code)?
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Since you didn't post your full code, I just put something together. I don't think it will matter whether or not lxn is an entity output or not. The only reason it's not is because the first run was simply to create code with no I/O and use the force statement to generate X and Y (which ran with no problem). The next step was to make the testbench which required the DUT to at least have inputs X and Y.
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Am I correct that your testbench avoids a delta cycle as X and Y change at exactly the same moment? What will happen if you induce a delta cycle by delaying the change of e.g. Y?
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What I asked though was to look at the values of X and Y in the list window as well. Are they actually changing on the exact same simulation delta cycle?
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I did put all stages in the list window and a saw nothing that would have generated the 261 value.
On my next 'try' I will add the report statement. I will then switch to Timing SImulation. As this design is heavily registered, most vital signals will be preserved and will allow a reasonably good inspection of the internals.
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