modelsim noob question?

Hi strykerg,

In general the registers in any FPGA (including Xilinx) start up with their values at zero, including the SRAMs which CAN be an issue (I'll explain later).

I was tempted to advise you to look at initial block but I thought it would be better for you to understand more of the Hardware approach.

Testbenches are an excellent way to get into the ins and outs of a language as they don't have to be compiled into the FPGA (however I have known of testbenches that were compiled into an FPGA). You will be able to learn about asserts and all of the System Commands.

My 'native' hardware language is VHDL which I use for home projects and I am presently using Verilog in my day job so I've become conversant with both.

While not 'dissing' Verilog you may want to consider VHDL, the reason being is that Verilog is like learning how to ride a bike without stabilisers, VHDL has all of the safeties turned on and will tell you when you do something odd, Verilog will just 'shrug' it's shoulders and let you crash and burn.

So take that on board.

Now as to the SRAMs being all at zero being a problem, this is because FPGAs are used to 'emulate' a real ASIC before it has been manufactured. This is to allow testing and SW development to start early. The problem is that sometimes the SW just assumes that memory contents will always be zero which in the real ASIC it won't be. To be fair the HW team sometimes also makes this mistake, that is a lot harder to fix than SW !

Anyway Good Luck in your endeavours :).

Best Regards

Andre'