Modelsim issue with included files

Hello,

I got a bench of verilog files that represents different modules. I made a top level verilog file that uses all the modules. Then, I have a bench of verilog files that contains many `define only. They are used to define parameters. Those files are included into the modules files.

I created a project with Quartus II, then I added all those files and defined the top-level file. The analysis & synthesis step is working fine.

Now, I'm trying to simulate my subsystem using Altera Modelsim. So, I ran the EDA RTL Simulation step. My issue comes now: It opens Modelsim window, then compiles the modules. But the modules require the include files that are used to define parameters, so it says : Cannot open `include file "path". Of course, the include files are not into the path directory, that's why it is not working. But I added those files in the Quartus II project as I said. I could add the include files to the directories targeted, but I suppose a better solution exists.

So ideally, what I would like to do with Modelsim : Execute include files, then compile the modules. But it doesn't execute include files.

Does sb know why ?

Best regards,

Julien