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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Modelsim issue with included files

Hello, I got a bench of verilog files that represents different modules. I made a top level verilog file that uses all the modules. Then, I have a bench of verilog files that contains many `def...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

the `includes are only used in simulation, not synthesis? in this case i don't think Quartus NativeLink will work properly.

try adding the "Cannot open" verilog files to the NativeLink window where you add the actual test bench file in Assignments > Settings > EDA Tools > Simulation.