Forum Discussion
K_T
New Contributor
New ContributorModelsim is not working with PCIe IP generated VHDL
I encounter problems for Cyclone V development. My design consist of 2 PCIe HIPs and some our logics. I am useing "Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" I simulate ou...
SengKok_L_Intel
Regular Contributor
Regular ContributorHi,
For the PCIe Cyclone V IP user guide, it is suggested to generate the example design/simulation model by using the Verilog. Therefore, the VHDL may not work in this case.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_c5_pcie_avmm.pdf
Regards -SK
