Honored ContributorI have a piece of wire that inverts a signal! On the pic that would have been attached if allowed, RSDI (pin 80) is connected to the D input of inst99. By the time the signal reaches the dffin node it has already been inverted. I have attached the Modelsim waves to show the RSDI and inst99 dffin waves. What am I missing?
Honored ContributorHi Ray:
I don't see any attachements. A wire should not invert the signal. Do you have the verilog/VHDL source on how the connection is made or are you using a schematic input method. It may be that the output you are using to drive the wire is already inverted. PeteHonored ContributorHi Pete - thanks for replying. I tried to attach a jpg, but unless it is a web-based image or a smilie I cannot see how to get it put up here. Here's the story so far: I am using pin 80 for serial data input, clocked in at around 5MHz. Modelsim shows the test data pattern on pin 80, 0xA535. This is linked using a wire in the schematic to the D input of a D-type flip flop (DFF). Modelsim shows this D-input (inst99/dffin) having inverted data 0x5ACA! I am fully expecting problems with clocking and garbled results from the Q output, but I really hoped that the signal would get to the D-input intact first. On the schematic the DFF can be right-clicked to give a properties box. In there it shows (albeit greyed out) that all ports have no additional inversion. The preset and clear are active low but this is not mentioned. Is there an easy way to get an attachment added to explain further? :confused: Ray
