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Altera_Forum's avatar
Altera_Forum
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12 years ago

modelsim inversion

I have a piece of wire that inverts a signal! On the pic that would have been attached if allowed, RSDI (pin 80) is connected to the D input of inst99. By the time the signal reaches the dffin node i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hi Ray:

I don't see any attachements. A wire should not invert the signal. Do you have the verilog/VHDL source on how the connection is made or are you using a schematic input method.

It may be that the output you are using to drive the wire is already inverted.

Pete