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Altera_Forum's avatar
Altera_Forum
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14 years ago

modelsim integer port type representation

hi there

i am a beginner in vhdl and modelsim -altera software

i have just a question about modelsim simulation :

i have this entity :

---------------------------------------------

entity adder is

port (a, b : in signed (3 downto 0);

c : out integer range -16 to 15);

end adder;

----------------------------------------------

architecture myarch of adder is

begin

c <= conv_integer(a+b);

end myarch;

----------------------------------------------

so my question is why on modelsim simulation waves window, when i add the "c" port, it is not in form of bits vector but just a variable ?

anyway to see the "c" port in form of vector of bits with the "c" port declaration as integer ?

quartus 2 create c[0],c[1],c[2],c[3],c[4] when i go in pin planner

and on modelsim i have just "c" and an object called "ww_c"

sorry for my english

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    You have to remember that VHDL has strong typing. So signed, unsigned, std_logic_vectors are arrays of std_logic. integer, is just an integer, it has no bits. Quartus converts an integer to actual bits to map it to hardware, but in VHDL there are no bits.

    I suggest that

    1. Do not use std_logic_arith library (its not part of the IEEE VHDL language standard.) Use numeric_std instead.

    2. use an array type when you want to see the actual bits.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    thx for the reply Tricky

    but why in modelsim-altera simulation wavesform i can't see the "c" integer type port as a vector of 5 elements like in quartus 2 simulation ?

    modelsim-altera represent this "c" port declared as integer in an object called "c" (just 1 element) and an other object called "ww_c" which is a vector of 5 elements

    what the "ww" mean in "ww_c" in modelsim ??
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Altera simulation is a netlist simulation, so you simulate after its been converted. You can do this in modelsim too.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    ok thx

    on modelsim-altera i use .vho and .sdo files for simulation

    what is the name extension .xxx of the netlist file generated by quartus II for modelsim-altera ? how i can simulate a netlist file on modelsim ?