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Altera_Forum
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14 years ago

modelsim integer port type representation

hi there i am a beginner in vhdl and modelsim -altera software i have just a question about modelsim simulation : i have this entity : --------------------------------------------- e...
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Altera_Forum
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14 years ago

You have to remember that VHDL has strong typing. So signed, unsigned, std_logic_vectors are arrays of std_logic. integer, is just an integer, it has no bits. Quartus converts an integer to actual bits to map it to hardware, but in VHDL there are no bits.

I suggest that

1. Do not use std_logic_arith library (its not part of the IEEE VHDL language standard.) Use numeric_std instead.

2. use an array type when you want to see the actual bits.