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I don't use any tristate in the design. I found out that the Z is caused by unused bits in internal signals(vector). I have no idea why does modelsim display unused bits in high Z condition.
eg.
reg [3:0] a ;
reg [3:0] b;
reg [7:0] result;
output reg [3:0] result_truncate;
result <= a * b;
result_truncate <= result[7:4];
the signal result[3:0] will be high Z.
How to set the modelsim to display the Z value as zero value?
from my past experience in using the modelsim, whenever deal with X, it always relate to uninitialized of signal if the X happen in the beginning of the simulation. It uses X instead of U. Besides, X also represents driver conflict when in the middle of simulation.
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Hi,
as far as I know all highlevel simulator will behave in this way. You have to keep in mind that you are simulating a netlist after synthesis. That means a lot of optimization are done on your design. The simulator indicates with "Z" that the net is not driven anymore. It should be a hint for you to look whether this is ok or not. Alternative the simulator could split the bus and remove all unused bits, but I never saw this behaviour.
Kind regards
GPK
Honored Contributor
