Altera_Forum
Honored Contributor
15 years agoModelSim error
Hi everyone...
I want to ask a question, In my VHDL design I manage to compile and simulate it using quartus simulator, it goes well. But when I tried to simulate it in ModelSim, I got an error messages like this : # ERROR! Vector Mismatch for output port done :: @time = 10 ns# Expected value = 0# Real value = U# ERROR! Vector Mismatch for output port P :: @time = 10 ns# Expected value = 0000000000000000# Real value = UUUUUUUUUUUUUUUU# ERROR! Vector Mismatch for output port P :: @time = 75 ns# Expected value = 1110110000000000# Real value = UUUUUUUUUUUUUUUU What does this mean?