Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

ModelSim error

Hi everyone... I want to ask a question, In my VHDL design I manage to compile and simulate it using quartus simulator, it goes well. But when I tried to simulate it in ModelSim, I got an err...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I assumed that I did that. Based on vaweform file (where I specified inputs) I got the testbench file. That testbench was used in ModelSim and I got posted error. What am I doing wrong?