ModelSim Error Undefined variable

Modelsim needs to be used to compile both source files, eg.

1) Create a work library

vlib work

vmap work [pwd]

2) Compile your source, eg., use the following form for each of your source files;

vcom vhdl_file.vhd

vlog verilog_file.v

vlog -sv systemverilog_file.sv

3) Compile your testbench

vlog verilog_tb.v

4) Run the testbench

vsim -t ps -novopt verilog_tb

add wave *

run -a

The GUI will have a similar procedure. Personally I use the command line.

Cheers,

Dave