ModelSim does not see the wires

I'm creating a project using a hierarchical schematic.

In a previous post I complained about the inability to monitor the internal signals.

Here's one solution...

I convert all the schematic files in the VHDL code. All schematic files were excluded from project

since the error:

Error (12049): Can't compile duplicate declarations of entity "zzz" into library "work"

After compiling

The testbench is generated automatically by PROCESSING/START/START_TEST_BENCH_TEMPLATE WRITER.

For button RTL simulator automatically starts the ModelSim.

In the hierarchical tree i1 shows all the internal signals (the names of the wires).

For the next iteration, I restore schematic and remove VHDL from project, I am doing the necessary changes, create new VHDL files

and start a new simulation.

Is this the only way to work with a hierarchical schematic design or are there ways to automate it?