modelsim does not generate clock signal

Hello,

I am trying to use testbenches in a big project. Quartus created tb itself and I just added a few lines within this testmodule:

initial begin

clk_clk = 0;

end

always# 10 clk_clk = ~clk_clk

Then by using RTL simulation I opened modelsim which added all wires of the project correctly but it is not simple generate clock

pic related

1) I did not find any explanation about grey lines. Why it even Pu0 (pull down?)

2) What did i wrong? I tried to follow altera RTL simulation guide

Looking forward any help :c i am very new to Quartus