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Altera_Forum's avatar
Altera_Forum
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7 years ago

modelsim does not generate clock signal

Hello, I am trying to use testbenches in a big project. Quartus created tb itself and I just added a few lines within this testmodule: initial begin clk_clk = 0; end always# 10 clk_...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

RTL simulation finally works! I used your guide and this helps!

Now i see it all the matter of names. I've used the name of TB file in native link settings, not the name, which Quartus gave to TB module.

Thank you a lot!