Altera_ForumHonored Contributor8 years agomodelsim clock network stuck StX (gate level sim) Hi All, I'm hoping someone can help with an issue I've observed in modelsim (10.5b, quartus 17.0). Simply put the clock network correctly drives the network right up to the point where it ...Show Moredataflow.jpg21 KB
Altera_ForumHonored Contributor8 years agoI will initialise d_reg to known value to keep modelsim happy
Recent DiscussionsTiming analysis - long combinational pathThe quartus license works with version 25.0 but not with version 17.0How can I use Quartus Pro 25.1 sopc-create-header-files tool to generate a jtag master header file?timing violation fixError (292014): Can't find valid feature line for core SLL_CA_HBC_T001_Hyperbus_Memory_Controller_10