Altera_ForumHonored Contributor8 years agomodelsim clock network stuck StX (gate level sim) Hi All, I'm hoping someone can help with an issue I've observed in modelsim (10.5b, quartus 17.0). Simply put the clock network correctly drives the network right up to the point where it ...Show Moredataflow.jpg21 KB
Altera_ForumHonored Contributor8 years agoI will initialise d_reg to known value to keep modelsim happy
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