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Altera_Forum
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9 years ago

modelsim ase 10.4d/quartus lite 16.0,15.1 on linux source font problem

I can't read vhdl/verilog source because of too small font around 1pt. tools->edit preference->source windows->fixed font or text font size setting change was no effect. This problem is same aft...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

I ran into this too in Ubuntu 16.04 LTS with modelsim 10.5 ASE. I fixed it as follows :

1. Open ~/.modelsim

2. Find: PrefDefault = ... textFontV2 {Verdana 12}

3. Change 12 to -12, so it will looks like this: textFontV2 {Verdana -12}

4. Save ~/.modelsim

5. Reopen modelsim