Modelsim and stratix 3 gate-level sim

I would appreciate any help with this error. I get this when I start the simulation in modelsim -

# Region: /tb_emif_mddr/u_asms_top/u_emif_top/u_sym_overlay_lut/sym_overlay_lut_rw16_r32/u_altmf_sym_lut/altsyncram_component

# ** Error: (vsim-3063) C:/projects/ivac/design/asms/syn/simulation/modelsim/asms_04.vo(25067): Port 'q_a_8' not found in the connected module (2nd connection).

# Region: /tb_emif_mddr/u_asms_top/u_emif_top/u_sym_overlay_lut/sym_overlay_lut_rw16_r32/u_altmf_sym_lut/altsyncram_component

# ** Error: (vsim-3063) C:/projects/ivac/design/asms/syn/simulation/modelsim/asms_04.vo(25067): Port 'q_a_7' not found in the connected module (3rd connection).

# Region: /tb_emif_mddr/u_asms_top/u_emif_top/u_sym_overlay_lut/sym_overlay_lut_rw16_r32/u_altmf_sym_lut/altsyncram_component

# ** Error: (vsim-3063) C:/projects/ivac/design/asms/syn/simulation/modelsim/asms_04.vo(25067): Port 'q_a_6' not found in the connected module (4th connection).

# Region: /tb_emif_mddr/u_asms_top/u_emif_top/u_sym_overlay_lut/sym_overlay_lut_rw16_r32/u_altmf_sym_lut/altsyncram_component

# ** Error: (vsim-3063) C:/projects/ivac/design/asms/syn/simulation/modelsim/asms_04.vo(25067): Port 'q_a_5' not found in the connected module (5th connection).

# Region: /tb_emif_mddr/u_asms_top/u_emif_top/u_sym_overlay_lut/sym_overlay_lut_rw16_r32/u_altmf_sym_lut/altsyncram_component

# ** Error: (vsim-3063) C:/projects/ivac/design/asms/syn/simulation/modelsim/asms_04.vo(25067): Port 'q_a_4' not found in the connected module (6th connection).

# Region: /tb_emif_mddr/u_asms_top/u_emif_top/u_sym_overlay_lut/sym_overlay_lut_rw16_r32/u_altmf_sym_lut/altsyncram_component

# ** Error: (vsim-3063) C:/projects/ivac/design/asms/syn/simulation/modelsim/asms_04.vo(25067): Port 'q_a_3' not found in the connected module (7th connection).

# Region: /tb_emif_mddr/u_asms_top/u_emif_top/u_sym_overlay_lut/sym_overlay_lut_rw16_r32/u_altmf_sym_lut/altsyncram_component

# ** Error: (vsim-3063) C:/projects/ivac/design/asms/syn/simulation/modelsim/asms_04.vo(25067): Port 'q_a_2' not found in the connected module (8th connection).

# Region: /tb_emif_mddr/u_asms_top/u_emif_top/u_sym_overlay_lut/sym_overlay_lut_rw16_r32/u_altmf_sym_lut/altsyncram_component

# ** Error: (vsim-3063) C:/projects/ivac/design/asms/syn/simulation/modelsim/asms_04.vo(25067): Port 'q_a_1' not found in the connected module (9th connection).

# Region: /tb_emif_mddr/u_asms_top/u_emif_top/u_sym_overlay_lut/sym_overlay_lut_rw16_r32/u_altmf_sym_lut/altsyncram_component

# ** Error: (vsim-3063) C:/projects/ivac/design/asms/syn/simulation/modelsim/asms_04.vo(25067): Port 'q_a_15' not found in the connected module (10th connection).

# Region: /tb_emif_mddr/u_asms_top/u_emif_top/u_sym_overlay_lut/sym_overlay_lut_rw16_r32/u_altmf_sym_lut/altsyncram_component

# ** Error: (vsim-3063) C:/projects/ivac/design/asms/syn/simulation/modelsim/asms_04.vo(25067): Port 'q_a_14' not found in the connected module (11th connection).

# Region: /tb_emif_mddr/u_asms_top/u_emif_top/u_sym_overlay_lut/sym_overlay_lut_rw16_r32/u_altmf_sym_lut/altsyncram_component

# ** Error: (vsim-3063) C:/projects/ivac/design/asms/syn/simulation/modelsim/asms_04.vo(25067): Port 'q_a_13' not found in the connected module (12th connection).

# Region: /tb_emif_mddr/u_asms_top/u_emif_top/u_sym_overlay_lut/sym_overlay_lut_rw16_r32/u_altmf_sym_lut/altsyncram_component

# ** Error: (vsim-3063) C:/projects/ivac/design/asms/syn/simulation/modelsim/asms_04.vo(25067): Port 'q_a_12' not found in the connected module (13th connection).

# Region: /tb_emif_mddr/u_asms_top/u_emif_top/u_sym_overlay_lut/sym_overlay_lut_rw16_r32/u_altmf_sym_lut/altsyncram_component

# ** Error: (vsim-3063) C:/projects/ivac/design/asms/syn/simulation/modelsim/asms_04.vo(25067): Port 'q_a_11' not found in the connected module (14th connection).

# Region: /tb_emif_mddr/u_asms_top/u_emif_top/u_sym_overlay_lut/sym_overlay_lut_rw16_r32/u_altmf_sym_lut/altsyncram_component

# ** Error: (vsim-3063) C:/projects/ivac/design/asms/syn/simulation/modelsim/asms_04.vo(25067): Port 'q_a_10' not found in the connected module (15th connection).

# Region: /tb_emif_mddr/u_asms_top/u_emif_top/u_sym_overlay_lut/sym_overlay_lut_rw16_r32/u_altmf_sym_lut/altsyncram_component

Here is the part of gate-level netlist that the error is referring to. You can see that the ports are there, then do I get this error? Any clues?

Thank you much.

Best regards,

Sanjay

---gate-level netlist---

altsyncram altsyncram_component(

.q_a({q_a_unconnected_wire_15,q_a_unconnected_wire_14,q_a_unconnected_wire_13,q_a_unconnected_wire_12,q_a_unconnected_wire_11,q_a_unconnected_wire_10,q_a_9,q_a_unconnected_wire_8,q_a_unconnected_wire_7,q_a_unconnected_wire_6,q_a_unconnected_wire_5,q_a_unconnected_wire_4,

q_a_unconnected_wire_3,q_a_unconnected_wire_2,q_a_unconnected_wire_1,q_a_0}),

.q_a_8(q_a_8),

.q_a_7(q_a_7),

.q_a_6(q_a_6),

.q_a_5(q_a_5),

.q_a_4(q_a_4),

.q_a_3(q_a_3),

.q_a_2(q_a_2),

.q_a_1(q_a_1),

.q_a_15(q_a_15),

.q_a_14(q_a_14),

.q_a_13(q_a_13),

.q_a_12(q_a_12),

.q_a_11(q_a_11),

.q_a_10(q_a_10),

.data_a({emif_write_data_15,emif_write_data_14,emif_write_data_13,emif_write_data_12,emif_write_data_11,emif_write_data_10,emif_write_data_9,emif_write_data_8,emif_write_data_7,emif_write_data_6,emif_write_data_5,emif_write_data_4,emif_write_data_3,emif_write_data_2,

emif_write_data_1,emif_write_data_0}),

.wren_a(valid_write_strobe_c),

.address_b({gnd,gnd,gnd,gnd,gnd,gnd,GND_port,gnd}),

.address_a({dsp_a_9,dsp_a_8,dsp_a_7,dsp_a_6,dsp_a_5,dsp_a_4,dsp_a_3,dsp_a_2,dsp_a_1}),

.clock0(wire_pll1_clk_2),

.devpor(devpor),

.devclrn(devclrn),

.devoe(devoe));

endmodule

module altsyncram (

q_a,

q_a_8,

q_a_7,

q_a_6,

q_a_5,

q_a_4,

q_a_3,

q_a_2,

q_a_1,

q_a_15,

q_a_14,

q_a_13,

q_a_12,

q_a_11,

q_a_10,

data_a,

wren_a,

address_b,

address_a,

clock0,

devpor,

devclrn,

devoe);

output [15:0] q_a;

output q_a_8;

output q_a_7;

output q_a_6;

output q_a_5;

output q_a_4;

output q_a_3;

output q_a_2;

output q_a_1;

output q_a_15;

output q_a_14;

output q_a_13;

output q_a_12;

output q_a_11;

output q_a_10;

input [15:0] data_a;

input wren_a;

input [7:0] address_b;

input [8:0] address_a;

input clock0;

input devpor;

input devclrn;

input devoe;

wire gnd = 1'b0;

wire vcc = 1'b1;

altsyncram_v9d2 auto_generated(

.q_a({q_a_unconnected_wire_15,q_a_unconnected_wire_14,q_a_unconnected_wire_13,q_a_unconnected_wire_12,q_a_unconnected_wire_11,q_a_unconnected_wire_10,q_a[9],q_a_unconnected_wire_8,q_a_unconnected_wire_7,q_a_unconnected_wire_6,q_a_unconnected_wire_5,q_a_unconnected_wire_4,

q_a_unconnected_wire_3,q_a_unconnected_wire_2,q_a_unconnected_wire_1,q_a[0]}),

.q_a_8(q_a_8),

.q_a_7(q_a_7),

.q_a_6(q_a_6),

.q_a_5(q_a_5),

.q_a_4(q_a_4),

.q_a_3(q_a_3),

.q_a_2(q_a_2),

.q_a_1(q_a_1),

.q_a_15(q_a_15),

.q_a_14(q_a_14),

.q_a_13(q_a_13),

.q_a_12(q_a_12),

.q_a_11(q_a_11),

.q_a_10(q_a_10),

.data_a({data_a[15],data_a[14],data_a[13],data_a[12],data_a[11],data_a[10],data_a[9],data_a[8],data_a[7],data_a[6],data_a[5],data_a[4],data_a[3],data_a[2],data_a[1],data_a[0]}),

.wren_a(wren_a),

.address_b({address_b[1],address_b[1],address_b[1],address_b[1],address_b[1],address_b[1],address_b[1],address_b[1]}),

.data_b({address_b[1],address_b[1],address_b[1],address_b[1],address_b[1],address_b[1],address_b[1],address_b[1],address_b[1],address_b[1],address_b[1],address_b[1],address_b[1],address_b[1],address_b[1],address_b[1],address_b[1],address_b[1],address_b[1],address_b[1],address_b[1],address_b[1],address_b[1],address_b[1],address_b[1],address_b[1],address_b[1],address_b[1],

address_b[1],address_b[1],address_b[1],address_b[1]}),

.address_a({address_a[8],address_a[7],address_a[6],address_a[5],address_a[4],address_a[3],address_a[2],address_a[1],address_a[0]}),

.clock0(clock0),

.devpor(devpor),

.devclrn(devclrn),

.devoe(devoe));

endmodule