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Altera_Forum's avatar
Altera_Forum
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14 years ago

modelsim and custom radix

Hi,

I'm trying to define a custom radix in the wave.do file for a single signal of type std_logic. However, this definition doesn't seem to be recognized by modelsim: the signal is always displayed with a numeric value. Does anyone have any idea why ?

clock.vhd

---------

...

constant cAM : std_logic := '0';

constant cPM : std_logic := '1';

signal ampm : std_logic;

...

ampm <= cAM;

...

ampm <= cPM;

...

wave.do

-------

radix define radix_ampm {

"1'b0" "AM" -color "white",

"1'b1" "PM" -color "white",

-default hexadecimal

}

add wave -noupdate -radix radix_ampm /tb/clock/ampm

Thanks for your help,

P9

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    If I create a dummy signal of type std_logic_vector(0 downto 0) and assign ampm to it, I can see the right radix in modelsim. However, I'd like to avoid this kind of hack.

    signal dbg_ampm : std_logic_vector(0 downto 0);

    dbg_ampm(0) <= ampm;

    add wave -noupdate -radix radix_ampm /tb/clock/dbg_ampm
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    I can only guess it is because std_logic is such a basic type, and it is also not an array type.

    you may have a few workarounds.

    define your own am/pm type:

    type ampm_t is (am, pm);

    signal ampm : ampm_t;

    or use a boolean

    signal isam : boolean;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    For sure, if ampm is an isolated signal, this is definitely the way to go as the meaning of the signal is then unambiguous when reading the code.

    For what concerns the boolean, I'm afraid that true/false is not much more readable than '1'/'0' for what concerns an AM/PM indicator.

    However...

    what if it is an alias to a bit of a larger register ?

    -> Don't think it is possible.

    what if it is a port signal ?

    -> Would require the use of a package.

    all these what clauses require additional complexity just to overcome the lack of support of the radix for std_logic in modelsim. Then my dummy signal trick has the same effort penalty, if not less.

    Thanks anyways for the suggestions.