ModelSim ALTSYNCRAM Issues

I think the clue to this "error", is that its not an error, just a warning - hence the Warning at the start of he sentence. This is to do with how the ram behaves. Given you're using opposite edges of the same clock you wont ever get a read - during write clash. So you can safely ignore the warning (not an error).

Thank you for your reply.

For clarity, this doesn't happen for every module I try to simulate.

Here's one other module I'm trying to simulate that has this issue. So far, I've only managed to simulate one module which didn't try to infer RAM/ROM, which might somehow be significant. This is for an ALU with mult and add which stores some constants locally - I've edited it to operate without a clock hoping that might make a different (for the constant storage) but still no luck. I was originally running modelsim through quartus, but I am now running it separately with sv files added to a project. It is within this project I have managed to simulate another module (a PC with a stall command)

module ALU(
ALU_Func,
A,
B,
Out,
Cout,
//clk,
SW
);
//Input, Output and internal signals
input logic  ALU_Func;
input logic  A;
input logic  B;
input logic  SW;
//input logic clk;
output logic  Out;
output logic Cout;
logic  Multout;
logic  Addout;
logic  Addinterim;
logic  Const;
logic  A2;
//Conststore conststore(/*clk,*/ALU_Func,Const);
//Constant Store
always
begin
	case (ALU_Func)
		3'b000:
			begin
				Const <= 8'b01100000;
			end
			
		3'b001:
			begin
				Const <= 8'b01000000;
			end
			
		3'b010:
			begin
				Const <= 8'b11000000;
			end
			
		3'b011:
			begin
				Const <= 8'b01100000;
			end
			
		3'b100:
			begin
				Const <= 8'b00010100;
			end
			
		3'b101:
			begin
				Const <= 8'b11101100;
			end
			
		3'b110:
			begin
				Const <= 8'b00000000;
			end
			
		3'b111:
			begin
				Const <= 8'b00000000;
			end
			
	endcase
end
//Output Multiplex
always
begin
if (ALU_Func == 3'b000 | ALU_Func == 3'b001 | ALU_Func == 3'b010 | ALU_Func == 3'b011)
	begin
	Out = Multout;
	end
else if (ALU_Func == 3'b100 | ALU_Func == 3'b101 | ALU_Func == 3'b110)
	begin
		Out = Addout;
	end
else
	begin
		Out = SW;
	end
end
//Multiplier
always
begin
	Multout = Const * B;
end
//Adder and constant multiplex
always
begin
	if (ALU_Func == 3'b100 | ALU_Func == 3'b101 /*| ALU_Func == 3'b000| ALU_Func == 3'b001*/) //ALU_Funcs for the addition of b1 and b2
		A2 = Const;
	else
		A2 = A;
	{Cout,Addout} = {A2,A2} + {B,B}; 
end
endmodule

`timescale 1 us / 1 ns
module testbenchALU();
  
logic  ALU_Func;
logic  A;
logic  B;
logic  SW;
//logic clk;
logic  Out;
logic Cout;
ALU alu(ALU_Func,A,B,Out,Cout/*,clk*/,SW);
/*
initial
begin
clk = 0;
forever begin
# 10ns clk= 1;
# 10ns clk = 0;
end
end
*/
initial
begin
  ALU_Func = 3'b000;
  A = 8'h01;
  B = 8'h01;
  SW = 8'h02;
 # 10ns
  ALU_Func = 3'b001;
  A = 8'h01;
  B = 8'h01;
  SW = 8'h02;
 # 20ns
  ALU_Func = 3'b010;
  A = 8'h01;
  B = 8'h01;
  SW = 8'h02;
 # 20ns
  ALU_Func = 3'b011;
  A = 8'h01;
  B = 8'h01;
  SW = 8'h02;
 # 20ns
  ALU_Func = 3'b100;
  A = 8'h01;
  B = 8'h01;
  SW = 8'h02;
 # 20ns
  ALU_Func = 3'b101;
  A = 8'h01;
  B = 8'h01;
  SW = 8'h02;
 # 20ns
  ALU_Func = 3'b110;
  A = 8'h01;
  B = 8'h01;
  SW = 8'h02;
 # 20ns
  ALU_Func = 3'b111;
  A = 8'h01;
  B = 8'h01;
  SW = 8'h02;
 # 20ns
  ALU_Func = 3'b000;
  A = 8'h01;
  B = 8'h01;
  SW = 8'h02;  
  
  
end
endmodule

none of your always blocks have sensitivity lists - so they are going to loop forever - causing your lockup. you probably need to change it to

You are absolutely right - my always blocks should have been defined as always_comb, thank you :)