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Altera_Forum
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9 years ago

modelsim altera starter simulation error with altera IP

Hi, i get an error when i try to compile my design that uses a ram IP featuring altera_syncram_component The error is "Unresolved defparam reference to 'enable_force_to_zero' in altera_syn...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Apparently i am missing the 'altera_syncram_component' module or whatever it is . In my project libraries however there are altera_ver, altera_mf_ver, altera_lnsim_ver included....in those libraries i can find an altera_syncram module but not altera_syncram_component...

Attached is the source file where the simulator complains...i am not expert in verilog but i guess the altera_syncram_component's library is not found?