Modelsim Altera Starter & .tb

Yes modelsim window come out , and location of modelsim.

Now i want to simulate altpll with RTL and gate level. When i simulate with gate level (or rtl) my result is bad (see attached room). I modifie parameters and always same result.

And i don't want always create my input signal.

I want create a testbench file to create input file once. (see attached room)

i assign test bench file in "assignments/settings .../ simulation /compile testbench " (see attached room) And i run gate level : message : error loading design (see attached room)

I hope you understand my probleme and you can help me.

Thanks