Honored Contributor
Honored Contributoryes when i run RTL simulation , i have this info in quartus :
Info (22036): Successfully launched NativeLink simulation (quartus_sh -t "c:/altera/12.1/quartus/common/tcl/internal/nativelink/qnativesim.tcl" --rtl_sim "test_pll" "test_pll_top") Info (22036): For messages from NativeLink execution see the NativeLink log file D:/Projets electronique Quartus/Test_pll/test_pll_nativelink_simulation.rpt Info (22036): Successfully launched NativeLink simulation (quartus_sh -t "c:/altera/12.1/quartus/common/tcl/internal/nativelink/qnativesim.tcl" --rtl_sim "test_pll" "test_pll_top") Info (22036): For messages from NativeLink execution see the NativeLink log file D:/Projets electronique Quartus/Test_pll/test_pll_nativelink_simulation.rpt Info (22036): Successfully launched NativeLink simulation (quartus_sh -t "c:/altera/12.1/quartus/common/tcl/internal/nativelink/qnativesim.tcl" -gate_netlist "test_pll_top.vho" -gate_timing_file "test_pll_top_vhd.sdo" "test_pll" "test_pll_top") Info (22036): For messages from NativeLink execution see the NativeLink log file D:/Projets electronique Quartus/Test_pll/test_pll_nativelink_simulation.rpt I think i use NativeLink. I want create a testbench file to no always create my input signal. In my first , i create manually my input siganl and export waveform in vhdl testbench. In assignments/settings .../ simulation /compile testbench But i run rtl simulation error loading?
