Honored Contributor
Honored ContributorHello Dave. Thanks for replying again.
--- Quote Start --- Are these "other people" customers? --- Quote End --- No. I am a student and doing some research with a professor. I actually just need to get the waveform to show my professor, since he has asked for that. --- Quote Start --- That is not a testbench. That is a series of stimulus that *tests nothing*. Testbenches should provide stimulus, check responses, perform illegal activity and check that nothing incorrect occurred, etc. --- Quote End --- I get what you are saying. That definitely is the correct way to test a design. I am actually implementing a searching & learning algorithm and the only thing that I care about is how many steps a learning agent takes to reach a target. I included the total steps in the waveform (for RTL simulation), and checked that manually... And I am also not checking my design with invalid inputs, since basically I am just doing all these to show that the algorithm can be implemented in hardware. So I only set input variables in my "testbench". I wrote the code and tested it with RTL simulation in last summer. And then I was waiting for the professor to get a board to test it in hardware. But now my professor has changed his mind and requested me to run post synthesis simulation to verify everything. So I have no choice but to get the waveform to show him:( But by any means, I do appreciate your review and help. Thank you! David