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I need to get the gate level simulation run and show the waveform to some other people
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Are these "other people" customers?
Do you have a requirements document or specification for this component? Does your testbench test each aspect of the component?
Customers do not want to see waveforms, ultimately they could care less about them. How can they possibly tell from a waveform whether a particular bus protocol is being violated? They cannot, that is what a verification/test suite is for.
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I would really appreciate it if you would have a look at the testbench and point out errors that I made. Thanks a lot!
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Here's my critical review (don't take it personally, this is "business").
That is not a testbench. That is a series of stimulus that *tests nothing*. Testbenches should provide stimulus, check responses, perform illegal activity and check that nothing incorrect occurred, etc.
Use of your testbench with the RTL or gate-level netlist level will "test" absolutely nothing.
Don't be embarrassed by my comments. Everyone has to learn somewhere, and you were smart enough to ask for advice and help.
Take a look at the files and testbench provided with this Wiki tutorial
http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial The testbenches in this tutorial perform writes, reads, check values etc. However, these testbenches are *also* unacceptable (to paying customers). The testbenches are minimal, because they need to work with Modelsim-ASE (which lacks features like SVA).
If you have a customer for your IP, then you need them to provide you with a clear definition of what that IP is supposed to do. Your testbench would then test and confirm that the IP implements those requirements.
Cheers,
Dave
Honored Contributor
