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sorry I don't understand. by sims I am referring to rtl simulations
if it works in rtl simulations, and you are confident in your timing constraints (and is timing is closed), it should work in actual hardware
honestly timing analysis is key because that will expose stuff like cross-clock transfers and long combinatorial chains
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I thought you meant simvsion. I see what you are saying now. I understand what you guys told me. But the problem is that I need to get the gate level simulation run and show the waveform to some other people. I'm afraid that I can't just say it passes timing test and will work for post synthesis...
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