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Altera_Forum
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12 years ago

Modelsim-Altera Simulation Error: Memory Allocation Failure

Hello everyone, I am trying to run the gate level simulation for some VHDL code. I could run RTL simulation successfully. But I always get "Memory Allocation Failure" for gate level simulation....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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I'd suggest sticking with RTL simulation and use timing tools to achieve multi-corner closure. if it works in sims and you're confident in your constraints, it should work in synth

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Hello jderrick. Is sims separated from quartus/modelsim? I have only used it for transistor level simulation and have no idea how it works for FPGA simulation...Will it simulate the code on transistor level by default if I simply run it? Thanks!