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Hello everyone,
I am trying to run the gate level simulation for some VHDL code. I could run RTL simulation successfully. But I always get "Memory Allocation Failure" for gate level simulation. I have limited knowledge about quartus and VHDL and don't even know what can cause this error. I have been troubled by this problem for a week. Could someone please give me some help? Any idea is appreciated!
Thanks a lot!
David
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I agree 100% with Dave regarding the lengthy gate level simulation. In our practice we never dare to do gate level simulation even at module level, let alone project level. The gate level simulation technology is too slow and untested and so possibly immature.
functional simulation plus timing pass is almost enough but care is needed regarding the following:
timing at io is correct
any false path or multicycle need to be very carefully added and tested.
any buffering may overflow/underflow in real time
any inputs undriven in real time that may be floating
and few other exceptions. Thus real time testing is best practice after functional simulation.
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