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You are correct, in that a gate-level synthesis is what you are looking for. However, in my opinion, it is more important to spend time creating your RTL along with a good testbench (verification suite), and then synthesize example designs, making sure they are fully constrained. You're taking a little bit of a leap of faith, but in my experience I have had very few (perhaps one) problem that a gate-level netlist simulation confirmed (but did not resolve). I have had hardware issues that *do not* show up in any sort of simulation.
My advice is not to focus too much energy on the gate-level netlist issue. File a Service Request and hope you'll get a response. Chances are that since this is not an Altera tool, you won't get much help, and since its a free version of a Mentor tool, you won't get much help there either.
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I see. Thank you so much for sharing your experience. I understand that simulation can't expose all the problems for many cases. But at this moment, I can't get a board in short time and I do need to get my design verified for post synthesis. Would you please list some potential/common reasons for my problem, so that I can take a look at that and maybe get the problem solved if I am lucky enough :)
David
Honored Contributor
