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I don't have a board to test my design in hardware. That's why I want to run gate level simulation to test it.
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Gate level simulation takes a really really long time for complex designs and you don't really gain any insight. Keep in mind that it is still a simulation, so a bug in a gate-level component may not be reflected in hardware and vice versa. You should really get yourself an evaluation board with the device you plan on using in your own custom designs.
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As for timing, I got no red message in the TimeQuest Timing Analyzer Summary except the "unconstrained paths". So I guess that is fine.
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No, it might not be fine. Constrain everything (even if the constraint is to cut the path to tell TimeQuest you do not care about a particular path).
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Do you know what could be the reason and how to fix it? Thank you again!
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It could be any number of reasons. If you can consistently crash Modelsim with a design, then submit a service request with Altera directly.
Cheers,
Dave
Honored Contributor
