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Altera_Forum
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12 years ago

Modelsim-Altera Simulation Error: Memory Allocation Failure

Hello everyone, I am trying to run the gate level simulation for some VHDL code. I could run RTL simulation successfully. But I always get "Memory Allocation Failure" for gate level simulation....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hello Dave. Thanks for your reply. At this moment, I don't have a board to test my design in hardware. That's why I want to run gate level simulation to test it. As for timing, I got no red message in the TimeQuest Timing Analyzer Summary except the "unconstrained paths". So I guess that is fine. Do you know what could be the reason and how to fix it? Thank you again!

David