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Altera_Forum
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12 years ago

Modelsim-Altera Simulation Error: Memory Allocation Failure

Hello everyone, I am trying to run the gate level simulation for some VHDL code. I could run RTL simulation successfully. But I always get "Memory Allocation Failure" for gate level simulation....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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Could someone please give me some help? Any idea is appreciated!

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Don't do it. (You did say "any idea")

Seriously though, if your RTL simulation works fine, and your design passes timing, then test it in hardware. If it does not work in hardware, then sure, go back and see if the gate-level also fails, however, even that is no guarantee. Ultimately you need to run the design in hardware.

Cheers,

Dave