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Altera_Forum
Honored Contributor
Honored ContributorModelSim-Altera show error on compilation while Quartus not.
Quartus compile this code without any errors.
code.sv
`timescale 1 ns/ 1 nsmodule test013_LITERAL (
input A,
input B,
output C
);
struct{enum{IDLE,
SOME_STAGE_1} FSM;
logic some_register;
} first_machine;
struct{enum{IDLE,
SOME_STAGE_2} FSM;
logic some_register;
} second_machine;
assign C = A ^ B;
endmodule`timescale 1 ns/ 1 nsmodule testbench();
reg test_A;
reg test_B;
wire test_C;
test013_LITERAL DUT (.A(test_A),
.B(test_B),
.C(test_C));
initial begin
# 100
test_A = 0;
test_B = 0;
# 100
test_A = 1;
test_B = 0;
# 100
test_A = 0;
test_B = 1;
# 100
test_A = 1;
test_B = 1;
end
endmodule1 Reply
Altera_ForumHi,
--- Quote Start --- Can I write on SystemVerilog two structs in one module and then make enum in each struct with the same literal ("IDLE" for example)? Is another struct means another scope? If not can anyone describe what structs are used for? If yes can anyone describe to me how to win ModelSim-Altera? --- Quote End --- You can use two structs in one module but you can`t use the same enumeration constants between two different enumeration types (since two structs have individual scope) inside two different structs. No two enum types can use the same enumeration constants between them If you want to use the same enumeration constants between two different enumeration types, you'll have to create unique prefixes or suffixes for them (for example IDLE_1) Best Regards Vikas Jathar (This message was posted on behalf of Intel Corporation)
