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Altera_Forum
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11 years ago

ModelSim Altera SE 10.1e - Error with gate-level sim and test bench parameters

I have a generic Verilog HDL component that accepts up to two optional parameters. Everything synthesizes and the RTL simulations work as expected. The problem is, I can't run a gate-level simulati...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Why are you running a gate-level sim? Most users have gotten away from that completely and rely on RTL and static timing analysis. I'm not sure what a gate-level sim will tell you besides maybe a synthesis bug?

In larger/newer devices, you can't even run a timing sim and I don't believe you can do gate-level either. But in the older ones where you could, I thought you could write out a simulation model post-synthesis, which would save the actual fit time for each permutation of the parameters.