ModelSim-Altera exiting

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am I right in I read that Quartus can't nativly simulate VHDL??? Which means I must use ModelSim?

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The Quartus native simulator handles VHDL and Verilog source files just fine. It just doesn't support test benches. If you are using a test bench, you need a simulator like ModelSim.

I would much rather use the internal simulator.

I have v8.0 of the web edition. When I click on the button to specify a Simulator input file, no files show up in the dialog. Although it says it compiled with no errors (but with 4 warnings). The output files go into the project directory, right?

If you can't tell, I am new to this. I am used to uC's.

Thanks,

Kevin

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When I click on the button to specify a Simulator input file, no files show up in the dialog.

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The simulation input files are the stimulus files such as a vector waveform file. This is what the Quartus native simulator uses instead of a test bench.

For functional simulation, the source files are used when you run "Processing --> Generate Functional Simulation Netlist". For timing simulation, the source files are used for the compilation; the simulation uses a postcompilation netlist.

Ahhh. So, I have to make a stimulus file. I will give it a try.

Thanks!

Kevin