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It seems that Modelsim truncates additions inappropriately. It appears that it uses the left hand side of an assignment to truncate the result of an additiion, even if that is not the final value. In the code below, the addition gets truncated to the length of the left hand side of the assignment first, and then further right shifted. It should preserve a bit length of the longest term in the addition plus one bit (for the carry). The truncation should only happen at the actual assignment.
module sandbox;
reg [8:0] apple;
reg [7:0] banana;
initial beginbanana = 8'hff;
apple = (banana + 1'b1)>>1;
banana = (banana + 1'b1)>>1;
$display("%x %x", apple, banana);
end
endmodule
The output is
080 00
While I expected
080 80
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Though I sympathesise with ModelSim adding apples to bananas but the banana basket is only 8 bits so adding '1' causes overflow of basket and results in zeros which are then shifted to give zeros
Honored Contributor
